The present invention generally relates to electronics packaging, and more particularly, to pre-applied underfill dispensed on the die prior to flip chip assembly.
Flip chip assembly technology, wherein the integrated circuit (IC) chips are essentially flipped over and bonded to substrates using solderable interconnects, has seen rapid growth in semiconductor packaging in recent years. Alignment marks on the chip and the fiducial marks on the substrates are used for the fast automatic alignment between the chip and the substrate using a flip chip tool. The assembly of encapsulated flip chip circuit boards, however, remains a time consuming and expensive process. The key drivers for the demand for this technology are increased I/O connections enabling greater speed and shorter connections resulting in improved signal integrity.
In order for wafer level packaging to be successful, the flip chip tool must be able to align the IC chips (also referred to as a die) to the substrate. Normally, key features on the die and substrate are located using vision systems. These points are used as references in the alignment of the die and the substrate. Key features on the die are either fiducials or solder bumps. Key features on the substrate are either fiducials or bond pads. Two or more die may be stacked in a single package.
An IC substrate may comprise a number of layers. Some layers may comprise organic or ceramic dielectric material. Some layers may comprise conductors, such as traces, ground planes, and vias. An IC substrate may include an electronic component mounted on a surface of the substrate. The electronic component may be functionally connected to other elements of an electronic system through a hierarchy of conductors that include substrate traces, ground planes, and vias. The conductors may carry signals that are transmitted among the electronic components, such as ICs, of the system. An IC substrate may have a relatively large number of input/output (“I/O”) terminals (also called “lands”), as well as a large number of power and ground terminals or lands, on a surface of the IC substrate.
The underfill material, which occupies the space between the flipped IC chip and the IC substrate, is important for reliability of the flip chip packages. Underfill material supports the electrical connections, protects them from the environment, and reduces the thermomechanical stress on the flip chip connection. The main reason for the thermal mechanical stress is the difference in coefficients of thermal expansion (CTE) between the silicon chip (2.8 ppm/C) and the organic laminate (17 ppm/C). The CTE of the underfill material is targeted to be close to the CTE of the solder interconnect which typically ranges from 22 ppm/C (low lead and lead free solders) to 28 ppm/C (high lead solders). The high modulus of elasticity (8 to 12 GPa) of the underfill material rigidly links the silicon and laminate over the entire area of the silicon and distributes the CTE mismatched thermal mechanical stress between silicon and laminate over the entire bonded area, rather than allowing the thermal mechanical stress to be concentrated at the solder joint, and cause fatigue fracture. In order to reduce this CTE mismatch, underfill materials typically contain inorganic filler, such as silica. Generally, the higher concentration of inorganic filler in the underfill material, the higher the thermal conductivity, which is desirable for high heat transfer so as to remove heat during operation of the chips.
IBM invented the OBAR (Over Bump Applied Resin) method in which pre-applied underfill on the chip for flip chip assembly eliminates the stress induced failure of the back-end-of-line (BEOL) during the flip chip assembly process. However, when the underfill having a high concentration of inorganic filler is pre-applied on the chip, the alignment between the chip bumps and the substrates pads (or pre-solder bumps on the substrate) is very difficult because the OBAR covers the alignment marks and bumps on the chip making it difficult for alignment. The underfill, having the high concentration of inorganic filler material, is opaque or translucent at the intended thickness approximating the height of the bumps (i.e., interconnect), which makes the vision systems currently utilized for alignment less practical and prone to error.
Referring now to Prior Art FIGS. 1-3, there is shown top down photomicrographs of a representative flip chip prior and subsequent to application of an OBAR underfill material at a thickness of 85 microns. In prior art FIG. 1, the representative flip chip without the OBAR underfill material coated thereon shows the alignment mark as clearly visible which can be used for automatic alignment using an automated visual alignment tooling system. In Prior Art FIGS. 2 and 3, the flip chip surface including the alignment marks are coated with OBAR underfill material at a thickness of 85 microns approximating the height of the bumps on the chip. In prior art FIG. 2, the OBAR underfill material includes relatively small particle sizes of inorganic filler material whereas in Prior Art FIG. 3, the OBAR underfill material includes relatively fine particle sizes of inorganic filler material. In both cases, the alignment mark is no longer visible making automatic alignment using an automated visual alignment tooling system impractical. In Prior Art FIG. 2, the OBAR material is translucent, thereby diffusing light to the alignment mark such that the alignment mark is not clearly visible, and in Prior Art FIG. 3, the OBAR material is opaque. In both situations, alignment of the flip chip to a substrate using an automated visual alignment tool is not feasible.